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LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface DESCRIPTIO
The LTC(R)6912 is a family of dual channel, low noise, digitally programmable gain amplifiers (PGA) that are easy to use and occupy very little PC board space. The gains for both channels are independently programmable using a 3-wire SPI interface to select voltage gains of 0, 1, 2, 5, 10, 20, 50, and 100V/V (LTC6912-1 ); and 0, 1, 2, 4, 8, 16, 32, and 64V/V (LTC6912-2). All gains are inverting. The LTC6912 family consists of 2 matched amplifiers with rail-to-rail outputs. When operated with unity gain, they will also process rail-to-rail input signals. A half-supply reference generated internally at the AGND pin supports single power supply applications. Operating from single or split supplies from 2.7V to 10.5V total, the LTC6912-X family is offered in tiny SSOP and DFN-12 Packages.
, LTC and LT are registered trademarks of Linear Technology Corporation. SPI is a trademark of Motorola, Inc.
FEATURES

2 Channels with Independent Gain Control LTC6912-1: (0, 1, 2, 5, 10, 20, 50, and 100V/V) LTC6912-2: (0, 1, 2, 4, 8, 16, 32, and 64V/V) Offset Voltage = 2mV Max (-40C to 85C) Channel-to-Channel Gain Matching of 0.1dB Max 3-Wire SPITM Interface Extended Gain-Bandwidth at High Gains Wired-OR Outputs Possible (2:1 Analog MUX Function) Low Power Hardware Shutdown (GN-16 Only, 2A Max at 2.7V) Rail-to-Rail Input Range Rail-to-Rail Output Swing Single or Dual Supply: 2.7V to 10.5V Total Input Noise: 12.6nV/Hz Total System Dynamic Range to 115dB 16-Pin GN (SSOP) or 12-Pin DFN Package Options Data Acquisition Systems Dynamic Gain Changing Automatic Ranging Circuits Automatic Gain Control
APPLICATIO S

TYPICAL APPLICATIO
3V 12 V+
A Dual, Matched Low Noise PGA (16-Lead SSOP Package)
0.1F 14 V-
40
GAIN OF 64 GAIN OF 32 GAIN OF 16
VINA 1F
2 INA
OUT A
15
VOUTA = GAINA * VINA
30
3
GAIN (dB)
AGND
LTC6912-X
20 GAIN OF 8 GAIN OF 4 10 GAIN OF 2 GAIN OF 1
VINB
4 INB
OUT B
13
VOUTB = GAINB * VINB
0
SHDN 3-WIRE SPI INTERFACE CS/LD DATA CLK
5 6 7 8
CHB SHDN CS/LD DIN
CHA DGND DOUT 10 9
6912 TA01a
-10 0.1 1 10 100 1000 FREQUENCY (kHz) 10000
6912 TA01b
U
U
U
LTC6912-2 Frequency Response
VS = 2.5V VIN = 10mVRMS
6912f
1
LTC6912
ABSOLUTE
(Note 1)
AXI U RATI GS
Specified Temperature Range (Note 3) LTC6912C-1, LTC6912C-2 ..................-40C to 85C LTC6912I-1, LTC6912I-2 .....................-40C to 85C LTC6912H-1, LTC6912H-2 (GN-16 Only) .....................................-40C to 125C Storage Temperature Range ..................-65C to 150C UE Package ....................................... -65C to 125C Lead Temperature (Soldering, 10sec)................... 300C
Total Supply Voltage (V + to V -) ............................... 11V Input Current ...................................................... 10mA Operating Temperature Range (Note 2) LTC6912C-1, LTC6912C-2 ..................-40C to 85C LTC6912I-1, LTC6912I-2 .....................-40C to 85C LTC6912H-1, LTC6912H-2 (GN-16 Only) .....................................-40C to 125C
PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW INA AGND INB CS/LD DIN CLK 1 2 3 4 5 6 13 12 OUTA 11 V
-
LTC6912CDE-1 LTC6912IDE-1 LTC6912CDE-2 LTC6912IDE-2
10 OUTB 9 8 7 V+ DGND DOUT
UE12 PACKAGE 12-LEAD (4mm x 3mm) PLASTIC DFN EXPOSED PAD IS CONNECTED TO V - (PIN 13), MUST BE SOLDERED TO PCB
TJMAX = 125C, JA = 160C/W
DFN PART MARKING 69121 69122
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
U
U
W
WW U
W
ORDER PART NUMBER
TOP VIEW NC 1 INA 2 AGND 3 INB 4 SHDN 5 CS/LD 6 DIN 7 CLK 8 16 NC 15 OUT A 14 V - 13 OUT B 12 V + 11 NC 10 DGND 9 DOUT
LTC6912CGN-1 LTC6912IGN-1 LTC6912HGN-1 LTC6912CGN-2 LTC6912IGN-2 LTC6912HGN-2
GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 150C, JA = 120C/W
GN PART MARKING 69121 6912I1 6912H1 69122 6912I2 6912H2
6912f
LTC6912
GAI SETTI GS A D PROPERTIES
Table 1. LTC6912-1 GAIN SETTINGS AND PROPERTIES
UPPER/LOWER NIBBLE Q7 Q3 0 0 0 0 0 0 0 0 1 1 Q6 Q2 0 0 0 0 1 1 1 1 0 1 Q5 Q1 0 0 1 1 0 0 1 1 X X Q4 Q0 0 1 0 1 0 1 0 1 X X NOMINAL VOLTAGE GAIN Volts/Volt 0 -1 -2 -5 -10 -20 -50 -100 0 dB -120 0 6 14 20 26 34 40 -120 MAXIMUM LINEAR INPUT RANGE (VP-P) Dual 5V Supply 10 10 5 2 1 0.5 0.2 0.1 10 Not Used (Note 11) Single 5V Supply 5 5 2.5 1 0.5 0.25 0.1 0.05 5 Single 3V Supply 3 3 1.5 0.6 0.3 0.15 0.06 0.03 3 NOMINAL INPUT NOMINAL OUTPUT IMPEDANCE (k) IMPEDANCE () (Open) 10 5 2 1 1 1 1 (Open) Not Used 0.4 0.7 3.4 3.4 3.4 6.4 15 30 (Open)
Table 2. LTC6912-2 GAIN SETTINGS AND PROPERTIES
UPPER/LOWER NIBBLE Q7 Q3 0 0 0 0 0 0 0 0 1 1 Q6 Q2 0 0 0 0 1 1 1 1 0 1 Q5 Q1 0 0 1 1 0 0 1 1 X X Q4 Q0 0 1 0 1 0 1 0 1 X X NOMINAL VOLTAGE GAIN Volts/Volt 0 -1 -2 -4 -8 -16 -32 -64 0 dB -120 0 6 12 18.1 24.1 30.1 36.1 -120 MAXIMUM LINEAR INPUT RANGE (VP-P) Dual 5V Supply 10 10 5 2.5 1.25 0.625 0.3125 0.156 10 Not Used (Note 11) Single 5V Supply 5 5 2.5 1.25 0.625 0.3125 0.156 0.078 5 Single 3V Supply 3 3 1.5 0.75 0.375 0.188 0.094 0.047 3 NOMINAL INPUT NOMINAL OUTPUT IMPEDANCE (k) IMPEDANCE () (Open) 10 5 2.5 1.25 1.25 1.25 1.25 (Open) Not Used 0.4 0.7 3.4 3.4 3.4 6.4 15 30 (Open)
U
U
U
6912f
3
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Total Supply Voltage (VS) Supply Current Per Channel Both Amplifiers Active (Gain = 1) VS = 2.7V, VINA = VINB = VAGND VS = 5V, VINA = VINB = VAGND VS = 5V, VINA = VINB = 0V Both Amplifiers Inactive (State 1000) VS = 2.7V, VINA = VINB = VAGND VS = 5V, VINA = VINB = VAGND VS = 5V, VINA = VINB = 0V VS = 2.7V, VSHDN = 2.43V VS = 5V, VSHDN = 4.5V VS = 5V, VSHDN = 4.5V CONDITIONS

ELECTRICAL CHARACTERISTICS
MIN 2.7
C, I GRADES TYP MAX 10.5 1.75 2.0 2.25 150 200 265 0.3 3.6 20 12 60 20 100 30 190 10 50 15 90 20 180 27 35 2.75 3.0 3.5 255 325 750 2 10 50 30 110 40 170 50 260 20 80 30 160 40 250
MIN 2.7
H GRADE TYP MAX 10.5 1.75 2.0 2.25 150 200 265 0.3 3.6 20 12 50 20 90 30 80 10 50 15 80 20 180 27 35 3.0 3.25 3.75 280 350 750 5 10 50 35 125 45 190 60 290 25 90 35 175 45 270
UNITS V mA mA mA A A A A A A mV mV mV mV mV mV mV mV mV mV mV mV mA mA
Specifications for both the LTC6912-1 and the LTC6912-2
Supply Current Per Channel (Software Shutdown)
Total-Supply Current (Hardware Shutdown, GN-16 package only) Output Voltage Swing LOW (Note 4)
VS = 2.7V, RL = 10k tied to Midsupply Point VS = 2.7V, RL = 500 tied to Midsupply Point VS = 5V, RL = 10k tied to Midsupply Point VS = 5V, RL = 500 tied to Midsupply Point VS = 5V, RL = 10k tied to 0V VS = 5V, RL = 500 tied to 0V

Output Voltage Swing HIGH (Note 4)
VS = 2.7V, RL = 10k tied to Midsupply Point VS = 2.7V, RL = 500 tied to Midsupply Point VS = 5V, RL = 10k tied to Midsupply Point VS = 5V, RL = 500 tied to Midsupply Point VS = 5V, RL = 10k tied to 0V VS = 5V, RL = 500 tied to 0V

Output Short-Circuit Current (Note 5) AGND Open-Circuit Voltage (GN-16 package only) AGND (Common Mode) Input Voltage Range AGND Rejection (i.e., Common Mode Rejection or CMRR) Slew Rate
VS = 2.7V VS = 5V VS = Single 5V Supply, VSHDN = 0.5V VS = Single 5V Supply, VSHDN = 4.5V VS = Single 2.7V Supply VS = Single 5V Supply VS = 5V VS = 2.7V, VAGND = 1.1V to 1.6V VS = 5V, VAGND = -2.5V to 2.5V Gain = 1 VS = 5V, VOUTA = VOUTB = 1.1V to 3.9V VS = 5V, VOUTA = VOUTB = 1.4V Gain = 10 (-1), Gain = 8 (-2) VS = 5V, VOUTA = VOUTB = 1.1V to 3.9V VS = 5V, VOUTA = VOUTB = 1.4V
2.45 0.55 0.75 -4.3 55 55 60
2.5 2.65
2.55 1.6 3.65 3.2
2.45 0.55 0.7 -4.3 50 50 57
2.5 2.65
2.55 1.6 3.65 3.2
V V V V V dB dB
80 75 80 12 16 20 26
80 75 80 12 16 20 26 -120 -120
Power Supply Rejection Ratio (PSRR) VS =2.7V to 5V
V/s V/s V/s V/s dB dB
Signal Attenuation at Gain = 0 Setting Signal Attenuation in Software Shutdown
Gain = 0 (Digital Inputs 0000), f = 200kHz (State = 1000)

-120 -120
6912f
4
LTC6912
ELECTRICAL CHARACTERISTICS
PARAMETER SHDN Input High Voltage (GN-16 Package Only) SHDN Input Low Voltage (GN-16 Package Only) SHDN Pin 5, Input High Current (GN-16 Package Only) SHDN Pin 5, Input Low Current (GN-16 Package Only) CONDITIONS VS = Single 2.7V VS = Single 5V VS = 5V VS = Single 2.7V VS = Single 5V VS = 5V VS = Single 2.7V VS = Single 5V VS = 5V VS = Single 2.7V VS = Single 5V VS = 5V
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
MIN

C, I GRADES TYP MAX
MIN 2.43 4.5 4.5
H GRADE TYP
MAX
UNITS V V V
Specifications for both the LTC6912-1 and the LTC6912-2 2.43 4.5 4.5 0.27 0.5 0.5 0.2 1 1 0.2 1 1

0.27 0.5 0.5 0.2 1 1 0.2 1 1
V V V A A A A A A
Specifications for the LTC6912-1 ONLY Voltage Gain (Note 6) VS = 2.7V, Gain = 1, RL = 10k VS = 2.7V, Gain = 1, RL = 500 VS = 2.7V, Gain = 2, RL = 10k VS = 2.7V, Gain = 5, RL = 10k VS = 2.7V, Gain = 10, RL =10k VS = 2.7V, Gain = 10, RL = 500 VS = 2.7V, Gain = 20, RL = 10k VS = 2.7V, Gain = 50, RL = 10k VS = 2.7V, Gain = 100, RL = 10k VS = 2.7V, Gain = 100, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 5, RL = 10k VS = 5V, Gain = 10, RL = 10k VS = 5V, Gain = 10, RL = 500 VS = 5V, Gain = 20, RL = 10k VS = 5V, Gain = 50, RL = 10k VS = 5V, Gain = 100, RL = 10k VS = 5V, Gain = 100, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 5, RL = 10k VS = 5V, Gain = 10, RL = 10k VS = 5V, Gain = 10, RL = 500 VS = 5V, Gain = 20, RL = 10k VS = 5V, Gain = 50, RL = 10k VS = 5V, Gain = 100, RL = 10k VS = 5V, Gain = 100, RL = 500 -0.07 -0.11 5.94 13.85 19.7 19.55 25.75 33.5 39.2 37.3 -0.08 -0.11 5.95 13.8 19.8 19.6 25.78 33.5 39.3 37.75 -0.06 -0.10 5.95 13.8 19.78 19.68 25.78 33.65 39.4 38.6 0 -0.02 6.01 13.95 19.93 19.85 25.94 33.8 39.6 38.9 0.01 -0.01 6.02 13.96 19.94 19.87 25.94 33.84 39.7 39.2 0.01 0 6.02 13.96 19.94 19.91 25.95 33.87 39.8 39.5 0.07 0.07 6.08 14.05 20.1 20.05 26.1 34.05 40.0 39.7 0.08 0.07 6.09 14.1 20.1 20.1 26.08 34.1 40.1 39.85 0.08 0.08 6.09 14.1 20.08 20.05 26.08 34.05 40.2 39.9 -0.08 -0.13 5.93 13.8 19.65 19.35 25.65 33.40 39.0 36.20 -0.09 -0.13 5.94 13.78 19.75 19.45 25.75 33.4 39.1 36.6 -0.07 -0.11 5.94 13.79 19.75 19.58 25.73 33.60 39.25 37.6 0 -0.02 6.01 13.95 19.93 19.85 25.94 33.8 39.6 38.9 0.01 -0.01 6.02 13.96 19.94 19.87 25.94 33.84 39.7 39.2 0.01 0 6.02 13.96 19.94 19.91 25.95 33.87 39.8 39.5 0.07 0.07 6.08 14.05 20.1 20.05 26.1 34.05 40.0 39.7 0.08 0.07 6.09 14.1 20.1 20.1 26.08 34.1 40.1 39.85 0.08 0.08 6.09 14.1 20.08 20.05 26.08 34.05 40.2 39.9 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
6912f
5
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Channel-to-Channel Voltage Gain Match (Note 6) CONDITIONS VS = 2.7V, Gain = 1, RL = 10k VS = 2.7V, Gain = 1, RL = 500 VS = 2.7V, Gain = 2, RL = 10k VS = 2.7V, Gain = 5, RL = 10k VS = 2.7V, Gain = 10, RL = 10k VS = 2.7V, Gain = 10, RL = 500 VS = 2.7V, Gain = 20, RL = 10k VS = 2.7V, Gain = 50, RL = 10k VS = 2.7V, Gain = 100, RL = 10k VS = 2.7V, Gain = 100, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 5, RL = 10k VS = 5V, Gain = 10, RL = 10k VS = 5V, Gain = 10, RL = 500 VS = 5V, Gain = 20, RL = 10k VS = 5V, Gain = 50, RL = 10k VS = 5V, Gain = 100, RL = 10k VS = 5V, Gain = 100, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 5, RL = 10k VS = 5V, Gain = 10, RL = 10k VS = 5V, Gain = 10, RL = 500 VS = 5V, Gain = 20, RL = 10k VS = 5V, Gain = 50, RL = 10k VS = 5V, Gain = 100, RL = 10k VS = 5V, Gain = 100, RL = 500 Gain Temperature Coefficient (Note 6) VS = 5V, Gain = 1, RL = OPEN VS = 5V, Gain = 2, RL = OPEN VS = 5V, Gain = 5, RL = OPEN VS = 5V, Gain = 10, RL = OPEN VS = 5V, Gain = 20, RL = OPEN VS = 5V, Gain = 50, RL = OPEN VS = 5V, Gain = 100, RL = OPEN VS = 5V, Gain = 1, RL = OPEN VS = 5V, Gain = 2, RL = OPEN VS = 5V, Gain = 5, RL = OPEN VS = 5V, Gain = 10, RL = OPEN VS = 5V, Gain = 20, RL = OPEN VS = 5V, Gain = 50, RL = OPEN VS = 5V, Gain = 100, RL = OPEN f = 200kHz, VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 10, RL = 10k VS = 5V, Gain = 100, RL = 10k

ELECTRICAL CHARACTERISTICS
MIN -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -1.0 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -0.8 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -0.6
C, I GRADES TYP MAX 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 2 -1.5 -11 -30 -40 -70 -140 1 1 0.2 -1 -1 -3 -3 113 108 89 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 1.0 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 0.8 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 0.6
MIN -0.1 -0.1 -0.1 -0.15 -0.15 -0.2 -0.15 -0.15 -0.2 -1.5 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -1.2 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -0.9
H GRADE TYP 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 2 -1.5 -11 -30 -40 -70 -140 1 1 0.2 -1 -1 -3 -3 113 108 89
MAX 0.1 0.1 0.1 0.15 0.15 0.2 0.15 0.15 0.2 1.5 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 1.2 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 0.9
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C dB dB dB
6912f
Specifications for the LTC6912-1 ONLY
Channel-to-Channel Gain Temperature Coefficient Match (Gain Specified in dB's) (Note 6)
Channel-to-Channel Isolation (Note 7)
6
LTC6912
ELECTRICAL CHARACTERISTICS
PARAMETER Offset Voltage Magnitude (Internal Op-Amp, Note 8) Offset Voltage Magnitude Referred to INA or INB Pins (Note 8) Input Offset Voltage Drift, Internal Op Amp DC Input Resistance at INA or INB Pins (Note 9) DC VINA or VINB = 0V Gain = 0 State = 8, Software Shutdown Gain = 1 Gain = 2 Gain = 5 Gain > 5 Gain = 1 Gain = 2 Gain = 5 Gain = 10 Gain = 20 Gain = 50 Gain = 100 Gain = 1 Gain = 2 Gain = 5 Gain > 5

The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
CONDITIONS Gain = 1 Gain = 1 Gain = 10

MIN
C, I SUFFIXES TYP MAX 0.125 0.25 0.14 6 2 3.5 2
MIN
H SUFFIX TYP 0.125 0.25 0.14 10
MAX 3.5 6.5 4
UNITS mV mV mV V/C
Specifications for the LTC6912-1 ONLY
>10 >10 10 5 2 1 85 90 100 120 130 150 190 10 5 5 5 0.4 0.7 1.0 1.9 3.4 6.4 15 30 >1 18 33 8.9 15.6 11.1 8.3 7.4 7.0 6.7 6.3 50 16
>10 >10 10 5 2 1 95 100 110 130 140 160 200 10 5 5 5 0.4 0.7 1.0 1.9 3.4 6.4 15 30 >1 33 8.9 15.6 11.1 8.3 7.4 7.0 6.7 6.3 50
M M k k k k ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C M MHz VRMS VRMS VRMS VRMS VRMS VRMS VRMS VRMS
DC Input Resistance Drift at INA or INB Pins (Note 9)
DC Input Resistance Match RINA-RINB
DC Small Signal Output Resistance DC VINA or VINB = 0V at OUT A or OUT B Pins Gain = 0 Gain = 1 Gain = 2 Gain = 5 Gain = 10 Gain = 20 Gain = 50 Gain = 100 State = 8, Software Shutdown Gain Bandwidth Product Wideband Noise (Referred to Input) Gain = 100 f = 1kHz to 200kHz Gain = 0 (Output Noise only) Gain = 1 Gain = 2 Gain = 5 Gain = 10 Gain = 20 Gain = 50 Gain = 100

6912f
7
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Voltage Noise Density (Referred to Input) CONDITIONS f = 50kHz Gain = 1 Gain = 2 Gain = 5 Gain = 10 Gain = 20 Gain = 50 Gain = 100 Gain = 10, fIN = 10kHz, VOUT = 1VRMS Gain = 10, fIN = 100kHz, VOUT = 1VRMS Specifications for the LTC6912-2 ONLY Voltage Gain (Note 6) VS = 2.7V, Gain = 1, RL = 10k VS = 2.7V, Gain = 1, RL = 500 VS = 2.7V, Gain = 2, RL = 10k VS = 2.7V, Gain = 4, RL = 10k VS = 2.7V, Gain = 8, RL = 10k VS = 2.7V, Gain = 8, RL = 500 VS = 2.7V, Gain = 16, RL =10k VS = 2.7V, Gain = 32, RL = 10k VS = 2.7V, Gain = 64, RL = 10k VS = 2.7V, Gain = 64, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 4, RL = 10k VS = 5V, Gain = 8, RL = 10k VS = 5V, Gain = 8, RL = 500 VS = 5V, Gain = 16, RL = 10k VS = 5V, Gain = 32, RL = 10k VS = 5V, Gain = 64, RL = 10k VS = 5V, Gain = 64, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 4, RL = 10k VS = 5V, Gain = 8, RL = 10k VS = 5V, Gain = 8, RL = 500 VS = 5V, Gain = 16, RL = 10k VS = 5V, Gain = 32, RL = 10k VS = 5V, Gain = 64, RL = 10k VS = 5V, Gain = 64, RL = 500

ELECTRICAL CHARACTERISTICS
MIN
C, I GRADES TYP MAX
MIN
H GRADE TYP
MAX
UNITS
Specifications for the LTC6912-1 ONLY 35.6 24.8 19.1 16.7 16 15.4 15.1 -90 0.003 -82 0.008 -0.07 -0.11 5.94 11.9 17.8 17.65 23.8 29.7 35.4 34.15 -0.08 -0.1 5.95 11.85 17.85 17.65 23.85 29.70 35.5 34.6 -0.06 -0.1 5.95 11.9 17.85 17.80 23.85 29.85 35.65 35.15 0 -0.02 6.01 12.02 18.0 17.94 24.01 30.0 35.8 35.3 0 -0.01 6.02 12.02 18.01 17.96 24.02 30.02 35.9 35.6 0.01 0 6.02 12.03 18.02 17.99 24.03 30.0 36.0 35.8 0.07 0.07 6.08 12.12 18.15 18.15 24.25 30.2 36.2 36.0 0.08 0.08 6.09 12.15 18.15 18.15 24.15 30.2 36.25 36.0 0.08 0.08 6.09 12.15 18.15 18.15 24.15 30.2 36.20 36.10 -0.08 -0.13 5.93 11.88 17.75 17.50 23.75 29.65 35.15 33.40 -0.09 -0.12 5.94 11.83 17.83 17.50 23.80 29.65 35.40 33.8 -0.07 -0.11 5.94 11.88 17.83 17.73 23.82 29.8 35.55 34.45 35.6 24.8 19.1 16.7 16 15.4 15.1 -90 0.003 -82 0.008 0 -0.02 6.01 12.02 18.0 17.94 24.01 30.0 35.8 35.3 0 -0.01 6.02 12.02 18.01 17.96 24.02 30.02 35.9 35.6 0.01 0 6.02 12.03 18.02 17.99 24.03 30.0 36.0 35.8 0.07 0.07 6.08 12.12 18.15 18.15 24.25 30.2 36.2 36.0 0.08 0.08 6.09 12.15 18.15 18.15 24.15 30.2 36.25 36.0 0.08 0.08 6.09 12.15 18.15 18.15 24.15 30.20 36.20 36.10 nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz dB % dB % dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Total Harmonic Distortion
6912f
8
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Channel-to-Channel Voltage Gain Match (Note 6) CONDITIONS VS = 2.7V, Gain = 1, RL = 10k VS = 2.7V, Gain = 1, RL = 500 VS = 2.7V, Gain = 2, RL = 10k VS = 2.7V, Gain = 4, RL = 10k VS = 2.7V, Gain = 8, RL = 10k VS = 2.7V, Gain = 8, RL = 500 VS = 2.7V, Gain = 16, RL = 10k VS = 2.7V, Gain = 32, RL = 10k VS = 2.7V, Gain = 64, RL = 10k VS = 2.7V, Gain = 64, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 4, RL = 10k VS = 5V, Gain = 8, RL = 10k VS = 5V, Gain = 8, RL = 500 VS = 5V, Gain = 16, RL = 10k VS = 5V, Gain = 32, RL = 10k VS = 5V, Gain = 64, RL = 10k VS = 5V, Gain = 64, RL = 500 VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 1, RL = 500 VS = 5V, Gain = 2, RL = 10k VS = 5V, Gain = 4, RL = 10k VS = 5V, Gain = 8, RL = 10k VS = 5V, Gain = 8, RL = 500 VS = 5V, Gain = 16, RL = 10k VS = 5V, Gain = 32, RL = 10k VS = 5V, Gain = 64, RL = 10k VS = 5V, Gain = 64, RL = 500 Gain Temperature Coefficient (Note 6) VS = 5V, Gain = 1, RL = OPEN VS = 5V, Gain = 2, RL = OPEN VS = 5V, Gain = 4, RL = OPEN VS = 5V, Gain = 8, RL = OPEN VS = 5V, Gain = 16, RL = OPEN VS = 5V, Gain = 32, RL = OPEN VS = 5V, Gain = 64, RL = OPEN VS = 5V, Gain = 1, RL = OPEN VS = 5V, Gain = 2, RL = OPEN VS = 5V, Gain = 4, RL = OPEN VS = 5V, Gain = 8, RL = OPEN VS = 5V, Gain = 16, RL = OPEN VS = 5V, Gain = 32, RL = OPEN VS = 5V, Gain = 64, RL = OPEN f = 200kHz, VS = 5V, Gain = 1, RL = 10k VS = 5V, Gain = 8, RL = 10k VS = 5V, Gain = 64, RL = 10k Gain = 1

ELECTRICAL CHARACTERISTICS
MIN -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.2 -0.7 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.6 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.4
C, I GRADES TYP MAX 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 2 -4 -10 -24 -30 -40 -120 0 -0.5 0 0 -1 -4 -4 117 110 92 0.125 2 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.2 0.7 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.15 0.6 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.15 0.4
MIN -0.1 -0.1 -0.1 -0.15 -0.15 -0.2 -0.15 -0.15 -0.2 -1.0 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.8 -0.1 -0.1 -0.1 -0.15 -0.15 -0.15 -0.15 -0.15 -0.15 -0.6
H GRADE TYP 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 2 -4 -10 -24 -30 -40 -120 0 -0.5 0 0 -1 -4 -4 117 110 92 0.125
MAX 0.1 0.1 0.1 0.15 0.15 0.2 0.15 0.15 0.2 1.0 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.15 0.8 0.1 0.1 0.1 0.15 0.15 0.15 0.15 0.15 0.15 0.6
UNITS dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C dB dB dB
Specifications for the LTC6912-2 ONLY
Channel-to-Channel Gain Temperature Coefficient Match (Note 6)
Channel-to-Channel Isolation (Note 7)
Offset Voltage Magnitude (Internal Op-Amp, Note 8)
3.5
mV
6912f
9
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Offset Voltage Magnitude Referred to INA or INB Pins (Note 8) Input Offset Voltage Drift, Internal Op Amp DC Input Resistance at INA or INB Pins (Note 9) DC VINA or VINB = 0V Gain = 0 State = 8, Software Shutdown Gain = 1 Gain = 2 Gain = 4 Gain > 4 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 1 Gain = 2 Gain = 4 Gain > 4 DC VINA or VINB = 0V Gain = 0 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 State = 8, Software Shutdown Gain = 64 f = 1kHz to 200kHz Gain = 0 (Output Noise Only) Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64

ELECTRICAL CHARACTERISTICS
CONDITIONS Gain = 1 Gain = 8
MIN

C, I GRADES TYP MAX 0.25 0.14 6 3.5 2
MIN
H GRADE TYP 0.25 0.14 10
MAX 6.5 4
UNITS mV mV V/C
Specifications for the LTC6912-2 ONLY
>10 >10 10 5 2.5 1.25 85 90 95 120 130 140 170 10 5 5 5 0.4 0.7 1.0 1.9 3.4 6.4 15 30 >1 17 30 8.1 13.8 9.6 7.5 6.4 6.0 5.8 5.6 50 15
>10 >10 10 5 2.5 1.25 95 100 105 130 140 150 180 10 5 5 5 0.4 0.7 1.0 1.9 3.4 6.4 15 30 >1 30 8.1 13.8 9.6 7.5 6.4 6.0 5.8 5.6 50
M M k k k k ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C ppm/C M MHz VRMS VRMS VRMS VRMS VRMS VRMS VRMS VRMS
DC Input Resistance Drift at INA or INB Pins (Note 9)
DC Input Resistance Match RINA-RINB
DC Small Signal Output Resistance at OUT A or OUT B Pins

Gain Bandwidth Product Wideband Noise (Referred to Input)
6912f
10
LTC6912
The denotes the specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. VS = 5V, AGND = 2.5V, Gain = 1, RL = 10k to midsupply point, unless otherwise noted.
PARAMETER Voltage Noise Density (Referred to Input) CONDITIONS f = 50kHz Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 Gain = 32 Gain = 64 Gain = 8, fIN = 10kHz, VOUT = 1VRMS Gain = 8, fIN = 100kHz, VOUT = 1VRMS MIN C, I GRADES TYP MAX MIN H GRADE TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
Specifications for the LTC6912-2 ONLY 31.1 22.8 17 14.6 13.2 12.9 12.6 -84 0.006 -82 0.008 31.1 22.8 17 14.6 13.2 12.9 12.6 -84 0.006 -82 0.008 nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz nV/Hz dB % dB %
Total Harmonic Distortion
SERIAL I TERFACE SPECIFICATIO S
SYMBOL VIH VIL VOH VOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t1 t2 t3 t4 t5 t6 t7 t8 t9 PARAMETER Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage DIN Valid to CLK Setup DIN Valid to CLK Hold CLK Low CLK High CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK Low CLK High CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low CL = 15pF CL = 15pF Sourcing 500A Sinking 500A CONDITIONS

Digital I/O Logic Levels, All Digital I/O Voltage Referenced to DGND 2 0.8 V+ - 0.3 0.3 60 0 100 100 60 60 30 125 0 30 0 50 50 40 40 20 85 0 V V V V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6912f
Serial Interface Timing, V + = 2.7V ~ 4.5V, V - = 0V (Note 10)
Serial Interface Timing, V + = 4.5V ~ 5.5V, V - = 0V (Note 10)
U
U
MIN
TYP
MAX
UNITS
11
LTC6912
SERIAL I TERFACE SPECIFICATIO S
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 PARAMETER DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High CLK Low CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low
t1 CLK t9 DIN D3 D2 D31 D0 t5 CS/LD t8 DOUT D4 D3 D2 D31 D0 D7 * * * D4 CURRENT BYTE D3
6912 TD
CONDITIONS

Serial Interface Timing, Dual 4.5V ~ 5.5V Supplies (Note 10) 30 0 50 50 40 40 20 85 0 ns ns ns ns ns ns ns ns ns
CL = 15pF
t2
t4
PREVIOUS BYTE
Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: The LTC6912-1C and LTC6912-1I are guaranteed functional over the operating temperature range of -40C to 85C. The LTC6912-1H is guaranteed functional over the operating temperature range of -40C to 125C. Note 3: The LTC6912-1C is guaranteed to meet specified performance from 0C to 70C. The LTC6912-1C is designed, characterized and expected to meet specified performance from - 40C to 85C but is not tested or QA sampled at these temperatures. The LTC6912-1I is guaranteed to meet specified performance from -40C to 85C. The LTC6912-1H is guaranteed to meet specified performance from -40C to 125C. Note 4: Output voltage swings are measured as differences between the output and the respective supply rail. Note 5: Extended operation with output shorted may cause junction temperature to exceed the 150C limit for GN package and 125 for a DFN package is not recommended. Note 6: Gain is measured with a large signal DC test using an output excursion between approximately 30% and 70% of supply voltage.
12
U
U
MIN
TYP
MAX
UNITS

t3 t6 t7
D7 * * * D4
D3
Note 7: Channel-to-channel isolation is measured by applying a 200kHz input signal to one channel so that its output varies 1VRMS, and measuring the output voltage RMS of the other channel relative to AGND with its input tied to AGND. Isolation is calculated: IsolationB = 20 * log10(VOUTA/VOUTB) or IsolationA = 20 * log10(VOUTB/VOUTA) High channel-to-channel isolation is strongly dependent on proper circuit layout. See Applications Information. Note 8: Offset voltage referred to the INA or INB input is (1 + 1/|GAIN|) times the offset voltage of the internal op amp, where GAIN is the nominal gain magnitude. The typical offset voltage values are for 25C only. See Applications Information. Note 9: Input resistance can vary by approximately 30% part-to-part at a given gain setting. Note 10: Guaranteed by design, not subject to test. Note 11: States 13, 14 and 15 (binary 11xx) are not used. Programming a channel to states 8 or higher will configure that particular channel into a low power shutdown state. In addition, programming a channel into state 15 (binary 1111) will cause that particular channel to draw up to 20mA of supply current and is not recommended.
6912f
LTC6912 TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 Frequency Response
50 40 30 GAIN (dB) 20 10 0 -10 GAIN OF 100 GAIN OF 50 GAIN OF 20 GAIN OF 10 GAIN OF 5 GAIN OF 2 GAIN OF 1 CHANNEL-TO-CHANNEL GAIN MATCH (dB) VS = 5V VIN = 10mVRMS 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0.1 1 10 100 1000 FREQUENCY (Hz) 10000
6912 G02
GAIN OF 1
-3dB FREQUENCY (MHz)
1
10
100 1000 FREQUENCY (kHz)
LTC6912-1 Channel Isolation vs Frequency
125 CHANNEL-TO-CHANNEL ISOLATION (dB) 120 115 110 105 100 95 90 85 80 100 FREQUENCY (kHz)
6912 G04
VOLTAGE NOISE DENSITY (nV/HZ)
VS = 5V VOUT = 1VRMS GAIN OF 1 REJECTION (dB) GAIN OF 10
GAIN OF 100
LTC6912-1 Distortion vs Frequency with Light Loading
THD-AMPLITUDE BELOW FUNDAMENTAL (dB) RL = 10k V = 2.5V -55 S VOUT = 1VRMS (2.83)VP-P -60 -65 GAIN OF 100 -70 -75 GAIN OF 10 -80 GAIN OF 1 -85 -90 0 50 100 150 FREQUENCY (kHz) 200
6912 G07
THD-AMPLITUDE BELOW FUNDAMENTAL (dB)
-50
THD PLUS NOISE (dB)
UW
10000
6912 G01
LTC6912-1 Channel Gain Matching vs Frequency
VS = 5V VIN = 10mVRMS GAIN OF 100 GAIN OF 10 6
LTC6912-1 -3dB Bandwidth vs Gain Setting
VIN = 10mVRMS
VS = 5V 1 VS = 2.7V
1
10 GAIN (V/V)
100
6912 G03
LTC6912-1 Power Supply Rejection vs Frequency
90 80 70 60 50 40 30 20 10 1000 0 1 10 100 1000 FREQUENCY (kHz) 10000
6912 G05
LTC6912-1 Noise Density vs Frequency
VS = 5V GAIN = 1 100 GAIN OF 1 GAIN OF 10 GAIN OF 100 10
+SUPPLY -SUPPLY
1
VS = 2.5V TA = 25C INPUT REFERRED 1 10 FREQUENCY (kHz) 100
6912 G06
LTC6912-1 Distortion vs Frequency with Heavy Loading
-30 GAIN OF 100 -40 -50 GAIN OF 10 -60 -70 -80 -90 GAIN OF 1 RL = 500 VS = 2.5V VOUT = 1VRMS (2.83)VP-P 0 50 100 150 FREQUENCY (kHz) 200
6912 G08
LTC6912-1 THD Plus Noise vs Input Voltage
-30 -40 -50 -60 -70 -80 GAIN OF 10 GAIN OF 100
VS = 5V -90 RL = 10k fIN = 1kHz GAIN OF 1 BW = 22kHz -100 0.001 0.01 0.1 1 10 INPUT VOLTAGE (VP-P)
6912 G09
6912f
13
LTC6912 TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 Hardware Shutdown Total Supply Current vs Temperature
HARDWARE SHUTDOWN (GN-16 ONLY)
TOTAL SUPPLY CURRENT (A) TOTAL SUPPLY CURRENT (A)
10 VS = 5V
VS = 5V
TOTAL SUPPLY CURRENT (mA)
1 VS = 2.7V
VS = 3V
0.1 -50 -25
50 25 75 0 TEMPERATURE (C)
LTC6912-1 Gain Shift vs Temperature (Light Load)
0.10 0.05
GAIN CHANGE (dB)
GAIN CHANGE (dB)
0 -0.05 -0.10
GAIN OF 1 GAIN OF 10
-0.5 GAIN OF 100 -1.0
GAIN (dB)
GAIN OF 100 -0.15 -0.20 -0.25 -50 -25
50 25 75 0 TEMPERATURE (C)
LTC6912-2 Channel Gain Matching vs Frequency
0.100
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
0.075 0.050 0.025 0 -0.025 -0.050 -0.075 -0.100 1 10 GAIN OF 1 GAIN OF 8 GAIN OF 64
6.0
-3dB FREQUENCY (MHz)
CHANNEL-TO-CHANNEL ISOLATION (dB)
VS = 5V VIN = 10mVRMS RL = 10k
1000 100 FREQUENCY (kHz)
14
UW
VS = 5V 100
6912 G10
LTC6912-1 Software Shutdown Total Supply Current vs Temperature
700 BOTH AMPLIFIERS IN SOFTWARE SHUTDOWN 600 RL = 10k 500 400 300 200 100 -50 -25 VS = 2.7V VS = 5V 5.00
LTC6912-1 Total Supply Current vs Temperature (Both Amplifiers Active)
BOTH AMPLIFIERS 4.75 PROGRAMMED TO GAIN = 1 RL = 10k 4.50 4.25 VS = 5V 4.00 3.75 3.50 3.25 VS = 2.7V VS = 5V
125
50 25 75 0 TEMPERATURE (C)
100
125
3.00 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
6912 G11 6912 G12
LTC6912-1 Gain Shift vs Temperature (Heavy Load)
VS = 5V RL = 10k 0.5 VS = 5V RL = 500 0 GAIN OF 1 GAIN OF 10 30 40
LTC6912-2 Frequency Response
GAIN OF 64 GAIN OF 32 GAIN OF 16 20 GAIN OF 8 GAIN OF 4 10 GAIN OF 2 GAIN OF 1 VS = 5V VIN = 10mVRMS
0
100
125
-1.5 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
-10 1 10 100 1000 FREQUENCY (kHz) 10000
6912 G14a
6912 G13
6912 G14
LTC6912-2 -3dB Bandwidth vs Gain Setting
8.0 VS = 5V VS = 2.7V VIN = 10mVRMS 125 120 115 110 105 100 95 90 85
LTC6912-2 Channel Isolation vs Frequency
GAIN = 1 VS = 5V VOUT = 1VRMS
4.0
GAIN = 8
2.0
GAIN = 64
1.0 0.8 0.6 0.4
10000
6912 G15
1
10 GAIN (V/V)
100
6912 G16
80 100 FREQUENCY (kHz)
1000
6912 G17
6912f
LTC6912 TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Power Supply Rejection vs Frequency
90 80 70 VS = 5V GAIN = 1 100
VOLTAGE NOISE DENSITY (nV/Hz)
VS = 2.5V TA = 25C INPUT REFERRED
THD (AMPLITUDE BELOW FUNDAMENTAL) (dB)
REJECTION (dB)
60 50 40 30 20 10 0 1 10 1000 100 FREQUENCY (kHz) 10000
6912 G18
+SUPPLY -SUPPLY
LTC6912-2 Distortion vs Frequency with Heavy Loading (RL = 500)
THD (AMPLITUDE BELOW FUNDAMENTAL) (dB)
-30 -40 -50 GAIN = 8 -60 -70 -80 -90 GAIN = 1 VS = 2.5V VOUT = 1VRMS (2.83VP-P) GAIN = 64 -30 -40
TOTAL SUPPLY CURRENT (A)
THD + NOISE (dB)
0
50
100 150 FREQUENCY (kHz)
LTC6912-2 Software Shutdown Total Supply Current vs Temperature
800 BOTH AMPLIFIERS PROGRAMMED TO STATE = 8 700 R = 10k L 600 500 VS = 5V 400 300 200 100 -50 -25 VS = 2.7V VS = 5V 6.0 5.5 5.0
TOTAL SUPPLY CURRENT (mA)
TOTAL SUPPLY CURRENT (A)
GAIN CHANGE (dB)
50 25 75 0 TEMPERATURE (C)
UW
6912 G21
LTC6912-2 Noise Density vs Frequency
-50 -55 -60 -65 -70 -75 -80 -85 -90
LTC6912-2 Distortion vs Frequency with Light Loading (RL = 10k)
VS = 2.5V VOUT = 1VRMS (2.83VP-P)
GAIN = 1 GAIN = 8
GAIN = 64
10
GAIN = 64
GAIN = 8 GAIN = 1
1 1 10 FREQUENCY (kHz) 100
6912 G19
0
50
100 150 FREQUENCY (kHz)
200
6912 G20
LTC6912-2 THD + Noise vs Input Voltage
LTC6912-2 Hardware Shutdown Total Supply Current vs Temperature
HARDWARE SHUTDOWN (GN-16 ONLY) VS = 5V 10 VS = 5V
-50 -60
GAIN = 64 GAIN = 8
-70 -80 -90 VS = 5V RL = 10k fIN = 1kHz 0.01 0.1 1 INPUT VOLTAGE (VP-P) 10
6912 G22
1 VS = 2.7V
GAIN = 1
VS = 3V
200
-100 0.001
0.1 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
6912 G22A
LTC6912-2 Total Supply Current vs Temperature (Both Amplifiers Active)
BOTH AMPLIFIERS ACTIVE : GAIN = 1 RL = 10k 0.100 0.075 VS = 5V 0.050 0.025 0 -0.025 -0.050 -0.075 -0.100 -0.125 3.5 3.0 -50 -25 -0.150 -0.175
LTC6912-2 Gain Shift vs Temperature (Light Load)
VS = 5V RL = 10k GAIN = 1
VS = 5V 4.5 4.0 VS = 2.7V
GAIN = 8
GAIN = 64
100
125
50 25 75 0 TEMPERATURE (C)
100
125
-0.200 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
6912 G23
6912 G24
6912 G25
6912f
15
LTC6912 TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Gain Shift vs Temperature (Heavy Load)
0.25 GAIN = 1 VS = 5V RL = 500
GAIN CHANGE (dB)
PI FU CTIO S
INA, INB: Analog Inputs. The input signal to the A channel amplifier of the LTC6912-X is the voltage difference between the INA pin and AGND pin. Likewise, the input signal to the B channel amplifier of the LTC6912-X is the voltage difference between the INB pin and AGND pin. The INA (or INB) pin connects internally to a digitally controlled resistance whose other end is a current summing point at the same potential as the AGND pin (Figure 1). At unity gain, the value of this input resistance is approximately 10k and the INA (or INB) pin voltage range is rail-to-rail (V+ to V-). At gain settings above unity, the input resistance falls. The linear input range at INA and INB also falls inversely proportional to the programmed gain. Tables 1 and 2 summarize this behavior. The higher gains are designed to boost lower level signals with good noise performance. In the "zero" gain state (state = 0), or in software shutdown (state = 8) analog switches disconnect the INA or INB pin internally and this pin presents a very high input resistance. In the "zero" gain state (state = 0), the input may vary from rail to rail but the output is insensitive to it and is forced to the AGND potential. Circuitry driving the INA and INB pins must consider the LTC6912-X's input resistance, its process variance, and the variation of this resistance from gain setting to gain setting. Signal sources with significant output resistance may introduce a gain error as the source's output resistance and the LTC6912X's input resistance forms a voltage divider. This is especially true at higher gain settings where the input resistance is the lowest. In single supply voltage applications, the LTC6912-X's DC ground reference for both input and output is AGND, not V -. With increasing gains, the LTC6912-X's input voltage range for an unclipped output is no longer rail-to-rail but diminishes inversely to gain, centered about the AGND potential.
NC INA 1 2 INPUT R ARRAY V+ - 100k AGND 3 100k V- MOS INPUT OP AMP + 13 OUT B - MOS INPUT OP AMP + 15 OUT A 14 V - 16 NC
16
UW
0
GAIN = 8 -0.25 GAIN = 64 -0.50
-0.75
-1.00 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
6912 G26
U
U
U
FEEDBACK R ARRAY
INB
4 INPUT R ARRAY CHANNEL A
12 V+ FEEDBACK R ARRAY CHANNEL B
11 NC
LOWER NIBBLE
8-BIT LATCH
UPPER NIBBLE V+
10 DGND
9 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER
DOUT
SHDN CS/LD DATA CLK
5 6 7 8
6912 BD
Figure 1. GN-16 Block Diagram
6912f
LTC6912
PI FU CTIO S
AGND: Analog Ground. The AGND pin is at the midpoint of an internal resistive voltage divider, developing a potential halfway between the V + and V - pins. In normal operation, the AGND pin has an equivalent input resistance of nominally 50k (Figure 1). In order to reduce the quiescent supply current in hardware shutdown (SHDN pin pulled to V +, GN-16 only), the equivalent series resistance of this pin significantly increases (to a value on the order of 800k with 5V supplies, but is highly supply voltage, temperature, and process dependent). AGND is the noninverting input to both the internal channel A and channel B amplifiers. This makes AGND the ground reference voltage for the INA, INB, OUTA, and OUTB pins. Recommended analog ground plane connection depends on how power is applied to the LTC6912-X (See Figures 2, 3, and 4). Single power supply applications typically use V - for the system signal ground. The analog ground plane in single-supply applications should therefore tie to V -, and the AGND pin should be bypassed to this ground plane by a high quality capacitor of at least 0.1F (Figure 2). The AGND pin provides an internal analog reference voltage at half the V+ supply voltage. Dual supply applications with symmetrical supplies (such as 5V) have a natural system ground plane potential of zero volts, in which the AGND pin can be directly tied to, making the zero volt ground plane the input and output reference voltage for the LTC6912-X (Figure 3). Finally, if dual asymmetrical power supplies are used, the supply ground is still the natural ground plane voltage. To maximize signal swing capability with an
ANALOG GROUND PLANE V+ REFERENCE 1 2 2 0.1F 3 4 5 6 SERIAL INTERFACE 7 8 16 LTC6912-X 15 14 13 12 11 10 9 DIGITAL GROUND PLANE
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Figure 2. Single Supply Ground Plane Connection
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asymmetrical supply, however, it is often desirable to refer the LTC6912-X's analog input and output to a voltage equidistant from the two supply rails V + and V -. The AGND pin will provide such a potential when open-circuited and bypassed with a capacitor (Figure 4). In noise sensitive applications where AGND does not tie directly to a ground plane, as in Figures 2 and 4, it is important to AC-bypass the AGND pin. Otherwise channel to channel isolation is degraded, and wideband noise will enter the signal path from the thermal noise of the internal voltage divider resistors which present a Thevenin equivalent resistance of approximately 50k. This noise can reduce SNR by at least 15dB at high gain settings. An external capacitor from AGND to the ground plane, whose impedance is well below 50k at frequencies of interest, will filter and suppress this noise. A 0.1F high quality capacitor is effective for frequencies down to 1kHz. Larger capacitors will extend this suppression to lower frequencies. This issue does not arise in dual supply applications because the AGND pin ties directly to ground. In applications requiring an analog ground reference other than half the total supply voltage, the user can override the built-in analog ground reference by tying the AGND pin to a reference voltage with the AGND voltage range specified in the Electrical Characteristics Table. The AGND pin will load the external reference with approximately 50k returned to the half-supply potential. AGND should still be capacitively bypassed to a ground plane as noted above. Do not connect the AGND pin to the V - pin.
ANALOG GROUND PLANE 1 2 3 LTC6912-X 16 15 14 V - 13 12 V + 11 10 9 DIGITAL GROUND PLANE
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0.1F
0.1F V+
SINGLE-POINT SYSTEM GND
4 5 6 SERIAL INTERFACE 7 8
0.1F
SINGLE-POINT SYSTEM GND
Figure 3. Symmetrical Dual Supply Ground Plane Connection
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LTC6912
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ANALOG GROUND PLANE V+ + V- REFERENCE 1 2 2 0.1F 3 4 5 6 SERIAL INTERFACE 7 8 16 LTC6912-X 15 14 V - 13 12 V + 11 10 9 DIGITAL GROUND PLANE
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Figure 4. Asymmetrical Dual Supply Ground Plane Connection
SHDN (GN-16 ONLY): CMOS Compatible Logic Hardware Shutdown Input. The LTC6912-X has two shutdown modes. One is a software shutdown state which can be software programmed into either Channel A, Channel B, or both. The software shutdown, when programmed to a particular channel (state = 8), will disable that channel's amplifier and tri-state open its analog input and analog output. The serial interface, however is still active. A hardware shutdown occurs when the SHDN pin is pulled to the positive rail. In this condition, both amplifiers and serial interface are disabled. The SHDN pin is allowed to swing from V - to 10.5V above V -, regardless of V+ so long as the logic levels meet the minimum requirements specified in the Electrical Characteristics table. The SHDN pin is a high impedance CMOS logic input, but has a small pull-down current source (<10A) which will force SHDN low if the logic input is externally floated. On initial power up (with SHDN open), or coming out of the hardware shutdown mode (pulling SHDN to V -), both amplifiers are reset into the power-on reset state (software shutdown mode, state = 8) for both channels. CS/LD: TTL/CMOS Compatible Logic Input. When this pin is asserted low, the CLK pin is enabled, and the 8-bit shift register serially shifts the shift register contents and whatever data is present on the DIN pin into the shift register on the rising edge of CLK. On the rising edge of CS/LD, the contents of the shift register data are loaded into the eight bit latch which configures the gain state of both channel A and channel B amplifiers. A logic high on CS/LD inhibits the CLK signal internally to the IC.
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0.1F
DIN: TTL/CMOS Compatible Logic Serial Data Input. The serial interface is synchronously loaded MSB first via DIN on the rising edge of CLK with CS/LD asserted low.
SINGLE-POINT SYSTEM GND
0.1F
CLK: TTL/CMOS Compatible Logic Input. With CS/LD asserted low, the clock synchronizes the loading of the serial shift register on its rising and falling edges. Data is shifted in at DIN on the rising edge of CLK and is shifted out on DOUT on the falling edge of CLK. DOUT: TTL/CMOS Compatible Logic Output. The MSB of the shift register contents is shifted out at DOUT on the falling edge of CLK. The output at DOUT swings between V+ and DGND, and is rated to drive approximately 15pF. DGND: Digital Ground: The DGND pin defines the potential from which LOGIC levels VIH and VIL for the 3-wire serial digital interface are referenced. The recommended connection of DGND depends on how power is applied to the LTC6912 (See Figures 2, 3, and 4). (CAVEAT: Under no conditions is DGND to exceed either supply pins V + and V -, which could result in damage to the IC if not current limited.) Single power supply applications typically use V - for the system signal ground. The preferred connection for DGND is therefore V - (See Figure 2). Dual supply applications with symmetrical supplies (such as 5V) have a natural system ground potential of zero volts, in which the DGND pin can be tied to, making the zero volt ground plane the logic reference (Figure 3). Finally, if dual asymmetrical power supplies are used, the system ground is still the natural ground plane voltage. V-, V+: Power Supply Pins. The V + and V - pins should be bypassed with 0.1F capacitors to an adequate analog ground plane using the shortest possible wiring. Electrically clean supplies and a low impedance ground are important for the high dynamic range available from the LTC6912 (see further details under the AGND pin description). Low noise linear power supplies are recommended. Switching power supplies require special care to prevent switching noise coupling into the signal path, reducing dynamic range.
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LTC6912
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OUT A, OUT B: Analog Output. These pins are the output of the A and B channel amplifiers respectively. Each operational amplifier can swing rail-to-rail (V + to V -) as specified in the Electrical Characteristics table. For best performance, loading the output as lightly as possible will minimize signal distortion and gain error. The Electrical Characteristics table shows performance at output currents up to 10mA, and the current limits which occur when the output is shorted midsupply at 2.7V and 5V supplies. Output current above 10mA is possible but current-limiting circuitry will begin to affect amplifier performance at approximately 20mA. Long-term operation above 20mA output is not recommended. Do not exceed maximum junction temperature of 150C for a GN and 125C for a DFN package. The output will drive capacitive loads up to 50pF. Capacitances higher than 50pF should be isolated by a series resistor (10 or higher).
APPLICATIO S I FOR ATIO
Functional Description
The LTC6912-X is a small outline, wideband, inverting two-channel amplifier with voltage gains that are independently programmable. Each delivers a choice of eight voltage gains, configurable through a 3-wire serial digital interface, which accepts TTL or CMOS logic levels (See Figure 5). Tables 1 and 2 list the nominal gains for the LTC6912-1 and LTC6912-2 respectively. Gain control within the amplifier occurs by switching resistors from a matched array in or out of a closed-loop op amp circuit using MOS analog switches (Figure 1). The bandwidths of the individual amplifiers depend on gain setting. The Typical Performance Characteristics section shows measured frequency responses.
CHANNEL A CHANNEL B
RESET LE
8-BIT LATCH LOWER NIBBLE UPPER NIBBLE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
DIN CLK CS/LD SHDN
LSB 8-BIT SHIFT-REGISTER RESET
MSB DOUT
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Figure 5. Serial Digital Interface Block Diagram
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Description of the 3-Wire SPI Interface Gain control of each amplifier is independently programmable using the 3-wire SPI interface (see Figure 5). Logic levels for the LTC6912 3-wire serial interface are TTL/ CMOS compatible. When CS/LD is low, the serial data on DIN is shifted into an 8-bit shift-register on the rising edge of the clock, with the MSB transferred first. Serial data on DOUT is shifted out on the clock's falling edge. A rising edge on CS/LD will latch the shift-register's contents into an 8bit D-latch and disable the clock internally on the IC. The upper nibble of the D-latch (4 most significant bits), configure the gain for the B-channel amplifier. The lower nibble of the D-latch (4 least significant bits), configures the gain for the A-channel amplifier. Tables 1 and 2 detail the nominal gains and respective gain codes. Care must be taken to ensure CLK is taken low before CS/LD is pulled low to avoid an extra internal clock pulse to the input of the 8-bit shift-register (See Figure 5). DOUT is active in all states, therefore DOUT cannot be "wire-OR'd" to other SPI outputs. An LTC6912 may be daisy-chained with other LTC6912s or other devices having serial interfaces by connecting the DOUT to the DIN of the next chip while CLK and CS/LD remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS/LD signal is pulled high to update all of them simultaneously. Figure 6 shows an example of two LTC6912s in a daisy chained SPI
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LTC6912
APPLICATIO S I FOR ATIO
configuration. It is recommended the serial interface signals should remain idle in between data transfers in order to minimize digital noise coupling into the analog path. Power On Reset On the initial application of power, the power on reset state of both amplifiers is low power software shutdown (state = 8) (see Tables 1 and 2). In this state, both analog amplifiers are disabled and have their inputs and outputs opened. This will facilitate the application of using the device as a 2:1 analog MUX, in that the amplifier's outputs may be wired-OR together and the LTC6912 can alternately select between A and B channels. Care must be taken if the outputs are wired-OR'd to ensure the software shutdown state (state = 8) is always programmed in one of the two channels.
1 SINGLE-POINT SYSTEM GND 2 3 4 5 CS/LD P DATA CLK 6 7 8 SHDN CS/LD DIN DGND DOUT LTC6912-X
CLK
DIN
D15
D11
D10
CS/LD
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Figure 6. Two LTC6912s (Four PGAs) in Daisy Chain Configuration
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Timing Constraints Settling time in the CMOS gain-control logic is typically several nanoseconds and is faster than the analog signal path. When the amplifier gain changes, the limiting timing is analog. As with any programmable-gain amplifier, each gain change causes an output transient as the amplifier's output moves, with finite speed, toward a differently scaled version of the input signal. The LTC6912-X analog path settles with a characteristic time constant or time scale, , that is roughly the standard value for a first order band limited response: = 0.35/f-3dB See the -3dB BW vs Gain Setting graph in the Typical Performance Characteristics section.
ANALOG GROUND PLANE 16 15 14 V - 13 12 V + 11 10 9 0.1F 1 2 3 0.1F 4 5 6 7 8 SHDN CS/LD DIN DGND DOUT LTC6912-X 16 15 14 V - 13 12 V + 11 10 9 0.1F 0.1F DIGITAL GROUND PLANE D9 D8 D7 D3 D2 D1 D0
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LTC6912
APPLICATIO S I FOR ATIO
Offset Voltage vs Gain Setting
The electrical tables list DC offset (error), VOS(OA), at the inputs of the internal op amp (See Figure 1). The electrical tables also show the resulting, gain dependent offset voltage referred to the INA, or INB pins, VOS(IN). The two measures are related through the feedback/input resistor ratio, which equals the nominal gain-magnitude setting, |GAIN|: VOS(IN) = (1 + 1/|GAIN|) VOS(OA) Offset voltages at any gain setting can be inferred from this relationship. For example, an internal amplifier offset VOS(OA) of 1mV will appear referred to the INA, INB pins as 2mV at a gain setting of 1, or 1.5mV at a gain setting of 2. At high gains, VOS(IN) approaches VOS(OA). (Offset voltage is random and can have either polarity centered on 0V). The MOS input circuitry of the internal op amp in Figure 1 draws negligible input currents (less than 10A), so only VOS(OA) and the GAIN affect the overall amplifier's offset. AC-Coupled Operation Adding capacitors in series with the INA and INB pins converts the LTC6912-X into a dual AC-coupled inverting amplifier, suppressing the input signal's DC level (and also adding the additional benefit of reducing the offset voltage from the LTC6912-X's amplifier itself). No further components are required because the input of the LTC6912-X biases itself correctly when a series capacitor is added. The INA and INB analog input pins connect internally to a resistor whose nominal value varies between 10k and 1k depending on the version of LTC6912 used (see the rightmost column of Tables 1 and 2). Therefore, the low frequency cutoff will vary with capacitor and gain setting. If, for example, a low frequency corner of 1kHz (or lower) on the LTC6912-1 is desired, use a series capacitor of 0.16F or larger. 0.16F has a reactance of 1k at 1kHz, giving a 1kHz lower -3dB frequency for gain settings of 10V/V through 100V/V. If the LTC6912-1 is operated at lower gain settings with a 0.16F capacitor, the higher input resistance will reduce the lower corner frequency down to 100Hz at a gain setting of 1V/V. These frequencies scale inversely with the value of input capacitor used.
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Note that operating the LTC6912 family in "zero" gain mode (digital state 0000) open circuits both the INA and INB pins and this demands some care if employed with a series AC coupling input capacitor. When the chip enters the zero gain mode, the opened INA or INB pin tends to sample and freeze the voltage across the capacitor to the value it held just before the zero gain state. This can place the INA or INB pin at or near the DC potential of a supply rail. (The INA or INB pin may also drift to a supply potential in this state due to small leakage currents.) To prevent driving the INA or INB pin outside the supply limit and potentially damaging the chip, avoid AC input signals in the zero gain state with an AC coupling capacitor. Also, switching later to a non-zero gain value will cause a transient pulse at the output of the LTC6912-1 (with a time constant set by the capacitor value and the new LTC6912-1 input resistance value). This occurs because the INA and INB pins return to the AGND potential forcing transient current sourced by the amplifier output to charge the AC coupling capacitor to its proper DC blocking value. SNR and Dynamic Range The term "dynamic range" is much used (and abused) with signal paths. Signal-to-noise (SNR) is an unambiguous comparison of signal and noise levels, measured in the same way and under the same operating conditions. In a variable gain amplifier, however, further characterization is useful because both noise and maximum signal level in the amplifier will vary with the gain setting, in general. In the LTC6912-X, maximum output signal is independent of gain (and is near the full power supply voltage, as detailed in the swing sections of the Electrical Characteristics table). The maximum input level falls with increasing gain, and the input-referred noise falls as well (listed also in the table). To summarize the useful signal range in such an amplifier, we define dynamic range (DR) as the ratio of maximum input (at unity gain) to minimum input-referred noise (at maximum gain). This DR has a physical interpretation as the range of signal levels that will experience an SNR above unity V/V or 0dB. At a 10V total power supply, DR in the LTC6912-X (gains 0V/V to 100V/V), the DR is typically 115dB (the ratio of 9.9 VP-P, or 3.5VRMS, maximum input to the 6.3VRMS high gain input noise). The
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LTC6912
APPLICATIO S I FOR ATIO
SNR from an amplifier is the ratio of input level to inputreferred noise, and can be 108dB with the LTC6912 family at unity gain. Construction and Instrumentation Cautions Electrically clean construction is important in applications seeking the full dynamic range of the LTC6912 family of dual amplifiers. It is absolutely critical to have AGND either AC bypassed or wired directly using the shortest possible wiring, to a low impedance ground return for best channelto-channel isolation. Short, direct wiring minimizes parasitic capacitance and inductance. High quality supply bypass capacitors of 0.1F near the chip provide good
TYPICAL APPLICATIO
Low Noise AC Amplifier with Programmable Gain and Bandwidth Analog data acquisition can exploit band limiting as well as gain to suppress unwanted signals or noise. Tailoring an analog front end to both the level and bandwidth of each source maximizes the resulting SNR. Figure 7 shows a block diagram for a low noise amplifier with gain and bandwidth independently programmable over a 100:1 range. Channels A and B of the LTC6912-1 are used to independently control the gain and bandwidth respectively over a 100:1 range. The LT1884 dual op amp forms
GAIN CONTROL PGA VIN INA LTC6912-1 CHANNEL A R2 V R1 IN GAINA
C1 10F OUTA
R1 15.8k
-
1/2 LT1884
+
VOUT = GAINA
-3dB BANDWIDTH RANGE IS FROM
Figure 7. Block Diagram of an AC Amplifier with Programmable Gain and Bandwidth
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decoupling from a clean, low inductance power source. But several centimeters of wire (i.e., a few H of inductance) from the power supplies, unless decoupled by substantial capacitance (>10F) near the chip, can create a parasitic high-Q LC resonant circuit in the hundreds of kHz range in the chip's supplies or ground reference. This may impair circuit performance at those frequencies. A compact, carefully laid out printed circuit board with a good ground plane makes a significant difference in minimizing distortion. Finally, equipment to measure performance can itself introduce distortion or noise floors. Checking for these limits with wired shorts from INA to OUTA and INB to OUTB in place of the chip is a prudent routine procedure. an integrating lowpass loop with capacitor C2 to set the programmable upper corner frequency. The LT1884 also supports rail-to-rail output swings over the total supply voltage range of 2.7V to 10.5V. AC coupling through capacitor C1 establishes a fixed low frequency corner of 1Hz, which can be adjusted by changing C1. Alternatively, shorting C1 makes the amplifier DC coupled. If DC gain is not needed, the AC coupling cap C1 serves to suppress several error sources: any shift in DC levels, low frequency noise, and DC offset voltages (not including the LT1884's low internal offset).
R2 15.8k C2 1F 1M BANDWIDTH CONTROL PGA R GAINB INB LTC6912-1 CHANNEL B 1 TO 2R1C1 1 R2 )C2 2 ( GAINB OUTB R
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-
1/2 LT1884 VOUT
+
1/2 LT1884
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LTC6912
PACKAGE DESCRIPTIO
0.65 0.05
3.50 0.05 1.70 0.05 2.20 0.05 (2 SIDES)
0.25 0.05 3.30 0.05 (2 SIDES) 0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
.254 MIN
.0165 .0015
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270)
NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DE/UE Package 12-Lead Plastic DFN (4mm x 3mm)
(Reference LTC DWG # 05-08-1695)
4.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) 1.70 0.10 (2 SIDES) PIN 1 NOTCH
(UE12/DE12) DFN 0603
7
R = 0.115 TYP
0.38 0.10 12
PIN 1 TOP MARK (NOTE 6) PACKAGE OUTLINE
0.200 REF
0.75 0.05
6 0.25 0.05 3.30 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005
.189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.009 (0.229) REF
.150 - .165
.229 - .244 (5.817 - 6.198)
.150 - .157** (3.810 - 3.988)
.0250 BSC
1 .015 .004 x 45 (0.38 0.10) 0 - 8 TYP
.0532 - .0688 (1.35 - 1.75)
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7
8
.004 - .0098 (0.102 - 0.249)
.008 - .012 (0.203 - 0.305) TYP
.0250 (0.635) BSC
GN16 (SSOP) 0204
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LTC6912
TYPICAL APPLICATIO
CHANNEL A INPUT 1F
CHANNEL B INPUT
3-WIRE SPI INTERFACE
MUX OPERATION: IF THE LOWER NIBBLE (Q3, Q2, Q1, Q0) IS (1, 0, 0, 0) THEN OUTA IS IN TRI-STATE AND THE UPPER NIBBLE (Q7, Q6, Q5, Q4) CONTROLS THE ACTIVE CHANNEL B. IF THE UPPER NIBBLE IS (1, 0, 0, 0) THEN OUTB IS IN TRI-STATE AND THE LOWER NIBBLE CONTROLS ACTIVE CHANNEL A.
RELATED PARTS
PART NUMBER LT1228 LT1251/LT1256 LTC1564 LTC6910-1/-2/-3 LTC6911-1/-2 LTC6915 DESCRIPTION 100MHZ Gain Controlled Transconductance Amplifier 40Mhz Video Fader and Gain Controlled Amplifier 10kHz to 150kHz Digitally Controlled Filter and PGA Digitally Controlled Programmable Gain Amplifier in SOT-23 Dual Digitally Controlled Programmable Gain Amplifier in MSOP-10 Zero Drift Instrumentation Amp with Digitally Programmable Gain COMMENTS Differential Input, Continuous Analog Gain Control Two Input, One Output, Continuous Analog Gain Control Continuous Time, Low Noise 8th Order Filter and 4-Bit PGA Single Programmable Gain Amplifier, 3-Bit Parallel Digital Interface Dual Programmable Gain Amplifiers, 3-Bit Parallel Digital Interface Gains 0 - 4096V/V, 116dB CMRR
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
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A 2:1 PGA MUX
V+ 12 V+ 0.1F 14 V- 2 INA OUT A 15 VOUT (TO ADC) 3 AGND LTC6912-X 4 INB OUT B 13 SHDN CS/LD DATA CLK 5 6 7 8 CHB SHDN CS/LD DIN CHA DGND DOUT 10 9
6912 TA02
6912f LT/TP 0804 1K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 2004

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